Terminals for the next generation, that are based on Radio Access technologies like Long Term Evolution (LTE) or WiMax are using digital interfaces between a radio frequency (RF) circuit and a baseband (BB) circuit, which are usually built as Application Specific Integrated Circuits (ASICs). This interface shall transport the user data as well as all required control information from/to BB ASIC to/from RF ASIC. It shall be formed by only a few lines and shall be robust against interference, emit itself as less interference as possible and it shall consume only low power.
A common standard for interfacing is the DigRF standard specified by the Mobile Industry Processor Interface (MIPI) Alliance. This standard is available in version v3.09—in the following called DigRF v3—and in version 4—in the following called DigRF v4.
The Digital Radio Frequency (DigRF) standard specifies a digital serial interface, which replaces the analog interface in previous generation mobile handset architectures. The DigRF standard supports a variety of air standards, e.g. as defined by the 3GPP, but not limited to those. The physical layer of DigRF standard connects a radio frequency integrated circuit (RFIC) and a base band integrated circuit (BBIC) via high speed serial links. Independent transmit (Tx) and receive (Rx) differential signal pairs allow for concurrent bi-directional communication between an RFIC and a BBIC.
Usually, RFIC and BBIC are provided in separate packages. However, it would be beneficial to provide RFIC and BBIC in a single package or even as a single chip solution to decrease pin count and printed circuit board (PCB) area.
DigRF v3 is the 3G capable version of the DigRF standard (DigRF, Dual-Mode 2.5G/3G baseband/RFIC interface standard, 22 Nov. 2006, version 3.09), which supports raw data rates up to 312 Mbit/s which is sufficient for Wideband Code Division Multiple Access (WCDMA) with Rx diversity. It has one serial Rx link and one serial Tx link.
The system clock (SysClk) can be 13, 26, 19.2 or 38.4 MHz. The nominal data rate is either SysClk/4 (low speed), SysClk (medium speed) or 312 Mbit/s (high speed). The high speed data clock of 312 MHz is derived from the system clock in the BBIC and RFIC.
DigRF v3 standard specifies a physical layer and a protocol layer.
The DigRF v3 physical layer has a serializer and a line driver in Tx direction and a synchronization unit as well as a line receiver and deserializer in Rx direction.
The data exchange on the protocol layer over the DigRF interface is organized by means of frames having a sync field, a header and the payload. The sync pattern is 16 bits and the header 8 bits long. The header contains the data type (data, control, etc.) and payload size. The payload size can be selected to be 8, 32, 64, 96, 128, 256, 512 bits. The payload can include I and Q data or control data.
DigRF v3 provides logical channels for IQ data and control of the radio parts to higher software layers. The use of these Logical Channels is not determined in the standard.
A DigRF v4 interface is divided in multiple layers (see MIPI Alliance Standard for DigRF v4, current version is V01.00.00, http://www.mipi.org). The lowest layer is the physical layer—in the following simply called PHY—that is based on the M-PHY, which is also standardized by the MIPI alliance and reused for several standards. It defines the analog electrical characteristics for the high speed serial transmission as well as an 8b10b coding stage for easing the clock data recovery (CDR). The next layer is the DigRF protocol layer which provides several logical channels towards the next higher layer. A logical channel is used to transmit messages with a payload up to 256 byte, which are mapped to frames and concatenated to bursts by the protocol layer. The protocol layer respectively a protocol layer extension cares additionally about error protection, error detection and error handling.
The next higher layer—called DigRF programming model—cares about how to use the logical channel and gives more abstract requirements how to handle the data and control flow between BBIC and RFIC. This layer was not included in former versions or releases of the standard and shall improve interoperability between different vendors.
The DigRF v4 offers much more features and flexibility in terms of different speeds, variable termination modes, variable length of synchronization sequence etc. as well as better reliability in terms of bit error rate compared to DigRF v3.
This causes on the other side an increased complexity of the interface itself in comparison to DigRF v3 and an increased effort in controlling and monitoring the interface. To provide also enough data rate for multiple-input multiple-output (MIMO) systems, the standard supports several parallel differential lines, which operate in parallel and which can be switched on/off dynamically.
The DigRF v4 is not backwards compliant and in some respects totally different from its predecessor DigRF v3. Differences for higher layers between the versions are the services provided by the protocol. Such differences include:                Defined logical channels and usage        Maximum payload sizes        Time Accurate Strobe (TAS) accuracy        TAS payload (interface control)        
However, conventional DigRF systems have some shortcomings. In most platforms, either DigRF v3 or DigRF v4 is implemented. In a scalable architecture it makes sense to have also the DigRF version configurable either by a hardware option, which means that there are two designs one with DigRF v3 and one with DigRF v4, or by software options, what means both versions of the interface have to be physically available on the chip and one is selected by the software. In the case of hardware options, one of those can e.g. be selected in the production process e.g. by means of a fuse, as is commonly known to a person skilled in the art, or by a special selection pin which can, during operation, be set to 0 or 1 (resp. low or high level) to select one option.
That means in some configurations where for example only Global System for Mobile communication (GSM) or WCDMA is used, DigRF v3 may be sufficient, and in a configuration with high demands on data rates DigRF v4 can be deployed. The DigRF v3 is simpler and needs less area for implementation. Also the DigRFv3 has less power consumption as its successor.
In both DigRF versions the area and power consumption is mainly dominated by the physical layer.
In case BBIC and RFIC are integrated in the same package or even on the same die, DigRF loses its main advantages namely to provide a high data rate interface on a minimum pin count. When integrated in such a way, the limiting factor is not the pin count, but rather power consumption. The latter is, however, not addressed by DigRF.
Thus, conventional DigRF technology may lack sufficient flexibility.